Today, there are two most common hardware description languages: Verilog / SystemVerilog and VHDL. The instrument description languages themselves are fairly universal means, but is this always the case? And what can the “non-universality” of the instrument description language depend on?
The idea of writing this article arose during the synthesis of a single project in different development environments, as a result of which different results were obtained from each other. Since the initial module is quite voluminous, a smaller module test module was written to demonstrate the obtained results, but the synthesis of which caused the same warnings / errors. A 4-bit register with asynchronous reset was used as a test module, and Libero SoC 18.1, Quartus Prime 17.1, Vivado 2017.4.1 were chosen as development environments.
First, a variant of the description of such a module in the Verilog language is presented, the text of which is perceived correctly by the selected development environments:
module test1 ( input clk, input arst, input [3:0] data, output reg [3:0] q ); always @( posedge clk or negedge arst ) begin if ( ~ arst ) begin q <= 4'h0 ; end else begin q <= data ; end end endmodule
As a result of the synthesis of this module, the following schemes were obtained:
- Libero SoC v11.8
- Quartus Prime 17.1
- Vivado 2017.4.1
On all synthesized circuits for test1, D-triggers were used with either an inverse reset input (Quartus Prime) or an inverter added (VERIFIC_INV in the case of Libero SoC and LUT1 in the case of Vivado).
Will the synthesized scheme be different if I change the asynchronous reset state check? To do this, you need to change the text of the test1 module to the description of the test2 module:
module test2 ( input clk, input arst, input [3:0] data, output reg [3:0] q ); always @(posedge clk or negedge arst) begin if (arst) begin q<=data; end else begin q<=4'h0; end end endmodule
It can be assumed that the synthesis of the test2 module should not differ from the synthesis of the test1 module, since the logic of the description of both modules does not contradict each other. However, the synthesis of the test2 module led to the following results:
- Libero SoC v11.8
The scheme was synthesized, but the following warning message appeared in the messages “Edge and condition mismatch (CG136)”. This warning indicates a mismatch between the sensitivity list and the check of the reset condition. However, the synthesized scheme does not differ from the test1 module.
- Quartus Prime 17.1
Synthesis of the circuit failed with the error:
“Error (10200): Verilog HDL Conditional Statement error at test2.v (10):” The error text is similar to the warning given by Libero SoC. - Vivado 2017.4.1
The synthesis of the scheme was carried out with a warning:
“[Synth 8-5788] Register q_reg in module test has been set. This may cause simulation mismatches. Consider rewriting code ["/home/vlasovdv0111/project_1/project_1.srcs/sources_1/new/test2.v":10]". As in the Libero SoC and Quartus Prime environments, a similar warning was issued. In addition, the warning was told about a possible discrepancy between the results of modeling and work in the "hardware", as a result, it was proposed to rewrite the module code.
After describing the modules test1 and test2, an idea appeared to check what would happen if the following code was synthesized:
module test3 ( input clk, input arst, input [3:0] data, output reg [3:0] q ); always @(posedge clk or negedge arst) begin if (arst) begin q<=4'h0; end else begin q<=data; end end endmodule
The description of such a register is not logical, since the reset of triggers in this case occurs when the reset line is in an inactive state.
The results of the synthesis were as follows:
- Libero SoC v11.8
The synthesis of the circuit did not materialize with the error: “Logic for q [3: 0] does not match a standard flip-flop (CL123)”, thereby refusing to produce a synthesis circuit, citing the absence of the type of triggers necessary for the synthesis. - Quartus Prime 17.1
The circuit synthesis failed with the following error: "Error (10200): Verilog HDL Conditional Statement error at test3.v (9): . The text of this error does not differ from the error text for the test2 module. - Vivado 2017.4.1
The synthesis of the scheme was carried out without errors:
However, what will happen if we describe a module in which the sensitivity list does not contradict the verification of the reset condition, but at the same time the reset of triggers occurs when the reset line is inactive, as in the case of the test3 module description. The description of such test4 module is as follows:
module test4 ( input clk, input arst, input [3:0] data, output reg [3:0] q ); always @( posedge clk or negedge arst ) begin if ( ~ arst ) begin q <= data ; end else begin q <= 4'h0 ; end end endmodule
During the synthesis, the following results were obtained:
- Libero SoC v11.8
The synthesis of the scheme was carried out with a warning:
“Found the signal identified as the system clock which controls 4 sequential elements including q_1 [3]. Using this clock, it can be adversely affected by the design of the clock. (MT532). "
- Quartus Prime 17.1
As a result of the synthesis scheme, warnings were received:
«Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning (13310): Register "q[0]~reg0" is converted into an equivalent circuit using register "q[0]~reg0_emulated" and latch "q[0]~1"
Warning (13310): Register "q[1]~reg0" is converted into an equivalent circuit using register "q[1]~reg0_emulated" and latch "q[1]~1"
Warning (13310): Register "q[2]~reg0" is converted into an equivalent circuit using register "q[2]~reg0_emulated" and latch "q[2]~1"
Warning (13310): Register "q[3]~reg0" is converted into an equivalent circuit using register "q[3]~reg0_emulated" and latch "q[3]~1"»
All of the above warnings correspond to the use of latches instead of triggers.
- Vivado 2017.4.1
The synthesis of the scheme was realized with one warning:
“[Synth 8-5788] Register q_reg in module test has been set. This may cause simulation mismatches. Consider rewriting code ["/home/vlasovdv0111/project_1/project_1.srcs/sources_1/new/test.v":11]". The text of this error completely repeats the text of the error for the test2 module.
Of all the experiments described, we can draw the following conclusions:
- Verilog is a universal language for describing hardware, the limitations of which are the capabilities of the development environments themselves;
- To properly describe the hardware, you need to know the syntax of the language, as well as analyze the lists of warnings and errors that occur at each stage of the project.