We continue to consider the trace of printed circuit boards. I publish this article from my native city of Severodvinsk, with gratitude to my school teachers. The theme to which she is dedicated is basic, and therefore it is important to deal with it. Reflections in signal lines will be considered here and, as always, recommendations will be made to reduce signal distortion, including using various line matching techniques.
In the
previous article of the cycle, it was shown that the presence of cuts in the path of the return current increases the inductance of the signal circuit, which negatively affects the EMP level of the PCB. However, their negative impact does not end there (it is worth noting that there are situations when using cuts in the support layer reduces the EMP level of the printed circuit board, however they require great care in terms of control of return currents and cannot be recommended in general). The cutout, like other irregularities (vias, branching tracks, changing the width of the track or the distance from the reference layer, etc.) change the local impedance value (born instantaneous impedance) signal line. Any change in impedance along the signal propagation leads to a change in its amplitude and the appearance of a reflected signal propagating back to the source (Fig. 1).
The amplitudes of the forward and reverse signals relative to the source are determined only by the impedances Z
1 and Z
2 at a given frequency:
A minus sign in front of the coefficients will mean a 180 ° change in signal phase. Even if the signal line is homogeneous (homogeneity of the line is understood here and hereinafter as the constancy of the geometric parameters of its cross section) throughout its length, and its impedance is constant and referred to as characteristic impedance, reflection can occur not only in the line itself and at its ends - on the source side or on the load side. Consider a simple circuit (Fig. 2), in which both the resistance of the signal source and the load are not consistent with the wave resistance of the homogeneous line. In this case, reflections in the line occur repeatedly, gradually fading out, and lead to an interference pattern - the sum of the signals. The diagram of the formation of the reflected signals and the simulation results in the LTSpice for a stepped pulse signal with an amplitude of 1.2 V and a leading edge of 1 ns are also shown in the figure.
Note that the voltage at the input of the signal line during the signal propagation time (before the first reflection) is not equal to the voltage of the signal source V
S and is associated with it by the resistive divider coefficient
After multiple reflections from the ends of the lines, the voltage value on the load tends to a sum of a decreasing geometric progression equal to the voltage on the lower shoulder of the resistive divider.
Since in real conditions it is impossible to ensure the constancy of the impedance in the propagation path of a signal, reflections always occur. The question is, under what conditions do they lead to noticeable signal distortions? Consider again the example of the circuit shown in fig. 2, fixing the values of the signal source resistance, load and wave resistance of the line. Consequently, the amplitudes of the interfering signals included in the sum are also saved. However, in addition to the amplitudes of the signals A
i, the value of the sum depends on their time offsets τ
i :
where TD is the time of signal propagation in the line or the time delay of the line (eng transmission line delay). This value is determined by the length L of the signal line and the speed v of signal propagation in the line TD = L / v. We will reduce the time delay of the line - while the duration of the "shelves", when the signal value is constant, will also decrease. And when i + 1st reflected signal will arrive at the load immediately after reaching the i-th signal of its amplitude value, the shelves will disappear. Since the signal reaches its amplitude value in a time equal to the duration of the front t
R , the following should be done:
A further decrease in the time delay value will lead to the fact that the amplitude values of the pulsations (English ringing) will not be achieved. In the limiting case of an infinitely short line TD → 0, an oscillatory transient is absent. This leads to the conclusion that it is necessary to minimize the length of the line for critical signals, which was already mentioned in the
previous article in connection with a decrease in inductance. Of course, the real signal lines on the printed circuit board have a finite length, so the mathematical criterion for the smallness of the ripple value is the condition TD << t
R.R.1.
The practical condition for small distortions of a pulse signal with a front edge tR in the signal line with a time delay TD, is TD <1/5 ∙ t R. To estimate the length of the signal line, you can take v ≈ 15 cm / ns (for FR4), then the condition can be rewritten as L [cm] <3 ∙ t R [ns].
It is important to understand that the permissible degree of distortion must be determined either by the developer of the printed circuit board, or this parameter must be indicated to it as restrictive. In addition, the amplitude of the pulsations depends not only on the ratio between t
R and TD, but also on the degree of line mismatch. In the above recommendation, small distortions are understood as pulsations, the amplitude of which does not exceed about 10%. If the condition t
R > 5 ∙ TD is not fulfilled or if the requirement for pulsations is stricter, then there are three ways to reduce the resonance phenomena in the line:
- a decrease in TD (primarily due to a decrease in the length of the line),
- an increase in t R (reduction in the speed of signal switching),
- line matching (eng. termination).
The goal of all line matching methods (table 1) is to ensure that there are no reflections at one or both of its ends. None of the methods is ideal - each of them has its own advantages and disadvantages, while absolutely all methods lead to additional energy losses. Therefore, it is not recommended to resort to line matching before the minimum possible line length and signal switching speed are provided.
Table 1. Signal line matching methods.
| Name and scheme | Loss level | Comments |
|---|
 | low |  |
 | tall |  |
 | average |  |
 | average |  |
Notes:
(1) In a parallel circuit, a connection can be used to both the common wire and the power supply.
(2) Optimality here refers to the criterion for minimizing energy loss.
In the case where a signal line connects a signal source to a single load (point-to-point), both impedance matching on the source side and on the load side can be used. If there are several loads on the signal line (English multiload), then it is recommended to use matching on the load side. Examples of such schemes where the absence of signal distortion is always critical, a multi-distributed clocking scheme, a multipoint data bus, the organization of external memory with several chips, etc. In the English-language literature, short (English stub) and long (English branch) signal line branches are distinguished. . The advantage of short branches is that they may not have matching components at the end, but there is a limit to their length.
R.2.
Short taps from the signal line may be inconsistent, however, their length should be minimal and should not exceed the value at which TD STUB 1/5 ∙ t R.
Three main branching patterns of the signal line in N sections are shown in Fig. 3. A circuit with a short section (the criterion is the same as for a branch) before branching leads to an increased load on the signal source. If the area before branching is long, then it is necessary to increase the impedance of the branches. An increase in the wave resistance of the signal line on the same layer will require a decrease in its width, which may be a limitation. If we use a series resistor with resistance R = (N - 1) ∙ Z
0 , then it forms a voltage divider - and the signal amplitude at the load decreases V
LOAD = 1 / N ∙ V
IN . Obviously, each of the schemes is not without drawbacks (in addition to increasing the number of components used), therefore topology with branching (eng. Star topology) is recommended to be used only when using a topology with a main signal line and short branches from it (eng. daizy-chain topology) impossible.
In conclusion, it should be noted that the choice of matching the signal line is closely related to the circuitry of the printed circuit board, so if the developer is only responsible for the layout of the printed circuit board, the decision should be made together with the circuit engineer using the signaling line simulation (SPICE or specialized software). However, the question of the need to reconcile the line is always initiated by the developer of the printed circuit board in case of impossibility to ensure the required level of distortion by other means.
The article was first published in the journal "Components and Technologies" 2018, No. 3. The publication on Habr is coordinated with the editors of the journal.